Switched-capacitor circuits based on threshold detectors such as a comparator and a zero-crossing detector can operate at high speeds at more than an order of magnitude lower power consumption than traditional circuits. The primary source of inaccuracy in threshold detector based circuits is the output voltage overshoot that results from the finite delay of the threshold detector. The amount of the output overshoot is the ramp rate multiplied by the delay of the threshold detector. In high speed circuits, the ramp rate must be very high. For example, in 200 MS/s pipeline analog-to-digital converters, each half clock phase is only about 2 ns if non-overlapping clock requirements are included. Subtracting the preset time necessary for the operation of the threshold detector based circuits, approximately 1.5 ns remains. In a single phase threshold detector based circuits, the ramp must traverse the full scale of about 1V in 1.5 ns, giving a ramp rate of 0.66V/ns. At this high ramp rate, a typical 200 ps delay of the threshold detector results in 133 mV output overshoot.
With enough over-range and digital error-correction capability, even such a large overshoot only translates to constant input referred offset. In practice, however, the variation of the overshoot is the problem. The ramp rate and the delay may change with process and temperature, causing a process and temperature dependent overshoot. More troublesome is the overshoot variation with the output signal. The ramp is not perfectly linear due to the finite output resistance of the current source and nonlinear parasitic capacitance. Therefore, the ramp rate is typically a function of the output voltage. The overshoot, as a consequence, is also a function of the output voltage. This signal dependent overshoot gives similar effects to finite gain in op-amp based circuits, hence causes nonlinearity in the resulting circuit characteristic. In analog-to-digital converters, for example, differential nonlinearity (DNL) and integral nonlinearity (INL) result.
In order to reduce the overshoot and resulting nonlinearity, the basic principle of a two phase ramp technique was demonstrated in prior art. The prior art 2-phase ramp circuit is illustrated in FIG. 1, where the charge-transfer phase of a typical switched-capacitor circuits is shown. The capacitors 34 and 35 typically sample the input voltage in the preceding sampling phase. The capacitor 41 is the sampling capacitor of the next stage, for example, of a pipeline A/D converter. Two current sources, 11 and 12 produce the coarse and the fine ramps, respectively. During the coarse phase, the coarse current source 11 is enabled and charges the capacitor network consisting of capacitors 34, 35, and 41. The value of the current source 11 is chosen such that a fast up-ramp is obtained. Typically, the time allowed for the coarse phase is less than 50% of the half clock phase. When the threshold detector trips, the current source 11 is disabled. The coarse phase overshoot VOS1, as shown in FIG. 2, is the product between the coarse phase ramp rate and the delay td1 of the threshold detector 20. Due to the high rate of the ramp, the coarse phase overshoot, VOS1 shown in FIG. 2, can be large. The fine phase reduces the overshoot substantially. Immediately after the coarse phase, the fine current source 12 is enabled. When threshold crossing is detected during the fine phase, the sampling switch 30 is turned off, locking the sampled charge on the next stage capacitor 41.
The fine phase ramp can be made much slower than the first phase ramp because it only traverses the amount of the coarse phase overshoot rather than the full scale. The fine phase ramp rate can be further reduced by correcting for the coarse phase overshoot as shown in FIG. 3. Since the coarse phase overshoot VOS1 is largely constant, it can be corrected by shifting threshold of the threshold detector 20 down by the input referred overshoot VOC. In the prior art, this is accomplished by switching the reference input of the threshold detector to 20 VOC during the coarse phase by turning ON the switch 31 in FIG. 1 and turning OFF the switch 32 in FIG. 1, and returning the voltage to the common-mode voltage VCM during the fine phase by turning ON the switch 32 and turning OFF the switch 31. If VOC−VCM=VOS1, the coarse phase overshoot will be zero. In practice, a small amount of overshoot must be allowed during the coarse phase to ensure the ramp crosses the threshold voltage of the threshold detector 20 in the presence of the variation in the overshoot. This is accomplished by making VOC−VCM slightly smaller than VOS1. Since the remaining coarse phase overshoot is much smaller, the fine phase ramp can be made substantially slower, for example by an order of magnitude, than that of the coarse phase. As a consequence, for given delay of the threshold detector, the final output overshoot VOS2 is greatly reduced. This not only improves the input referred offset, but also improves the linearity between the input and output voltages of the circuit. In addition, the threshold detector input is better balanced during the threshold crossing detection, thus the power supply rejection is greatly improved. Although the input of the threshold detector is unbalanced during the coarse phase threshold detection, it poses no problem because any noise or error introduced during the coarse phase is removed during the fine phase.